1. Field of the Invention
The present invention relates to a method of correcting assist features, and more particularly, to a method of correcting assist features before performing an optical proximity correction (OPC) method which is used to modify an original layout pattern.
2. Description of the Prior Art
With the trend of miniaturization of electronic products and peripheral devices, research into thin structures and high integration of semiconductor devices has become a main concern in the industry. Lithography technology plays an important role in determining the performance of semiconductor devices.
In a semiconductor manufacturing process, the integrated circuit layout is first designed and formed as a mask pattern. The mask pattern is then proportionally transferred to a photoresist layer disposed on the semiconductor wafer through an exposure process followed by a development process. Subsequently, a corresponding etching process is performed in order to manufacture the semiconductor devices on the semiconductor wafer. With the demand of increasing integration of semiconductor devices, the design rule of line width and spaces between lines or devices becomes finer. However, due to the optical proximity effect (OPE), the width is subject to optical limitations. To obtain the fine-sized devices, the pitch i.e. the interval between transparent regions in a mask, is scaled down along with the device size. However, if the pitch is scaled down to a specific range (for example, equal to or smaller than half the wavelength of light used in the exposure process), when the light passes through the mask, diffraction and interference may occur. The resolution of the mask pattern transferred onto the photoresist layer will be affected; due to the OPE, deviations in the transferred pattern such as rounded right-angle corners, shortened line-ends, or increase/decrease of line widths may occur.
To overcome the above problems, the prior art utilizes assist features on the mask such as dummy patterns or scattering bars disposed between the layout patterns used to construct the integrated circuit (IC), for reducing the risk of deformation of the transferred pattern. Consequently, a way to form proper assist features which can be further used to assist accurate layout pattern formation on the target layer is an important issue in the field.